Epitaxial germanium on silicon is useful for extending conventional Si complementary metal-oxide-semiconductor (CMOS) circuits. It can be used to integrate fast germanium photo detectors and modulators on Si CMOS for optical interconnections. Furthermore, germanium shows only a small lattice mismatch with GaAs and can therefore be utilized as a virtual substrate for the integration of III-V devices on Si. Ge(111) layers can also be used for epitaxial growth of III-nitrides (such as GaN).
Besides extending conventional Si electronics, epitaxial germanium on silicon can enable the replacement of Si CMOS by Ge electronics for high performance applications. Germanium transistors can be faster, because of the higher carrier mobility. Using bulk germanium substrates for CMOS is not feasible, as there is insufficient material available to cover the market needs. However, by employing only a thin layer of germanium deposited on a suitable substrate, this problem can be avoided. An important advantage of using epitaxial growth of Ge on Si substrates is the scalability: germanium layers of larger diameter can be obtained by simply using larger Si substrates.
Epitaxial growth is mostly utilized to obtain a crystalline layer on top of another crystalline material. However, heteroepitaxial growth of germanium on silicon is rather difficult because of the large mismatch of 4% between the two lattices. This difference in lattice dimensions leads to island growth, causing high surface roughness and high density of threading dislocations (TDD) in the Ge layer. Additional annealing or chemical-mechanical-polishing (CMP) steps are often required to reduce the surface roughness. Obtaining high quality and smooth crystalline germanium, directly on silicon, is therefore challenging.
In semiconductor processing, substrate surface roughness is one of the key issues which degrade channel mobility in submicron transistor devices. In most applications, a rough surface complicates the processing into devices and leads to inferior devices compared to devices processed from smooth layers.
In general, roughness is a measurement of the small-scale variations in the height of a physical surface. This is in contrast to large-scale variations, which may be either part of the geometry of the surface or unwanted ‘waviness’. The Root Mean Square (RMS) is a statistical measure of the magnitude of these small-scale variations.
In IC processing Chemical Mechanical Polishing (CMP) techniques are used to improve the substrate surface roughness. However, for example in case of germanium, a RMS value for the surface roughness below 0.50 nm is very difficult to reach. Although this value meets the current requirements of the International Technology Roadmap for Semiconductors (ITRS), it is clear that as transistors are further downscaled, it will become more and more important to further improve the surface roughness in a simple and cost-efficient way.
A known method to form a mono-crystalline layer on a mono-crystalline substrate is Solid Phase Epitaxy (SPE). A mono-crystalline substrate is used to impose its structure onto an amorphous (highly disordered) layer deposited hereupon. Solid phase epitaxy is extensively used to create e.g. epitaxial silicides on crystalline silicon layers.
Solid phase epitaxy of pure germanium on Si(111) substrates has been reported for layers of a few nanometers thick deposited in ultra high vacuum. However this resulted in a high density of islands. Both epitaxy and solid phase epitaxy are dominated by the problem of large lattice mismatch between the mono-crystalline Ge layer and the substrate (Si) and show island growth leading to high surface roughness and high density of threading dislocations in the Ge layer. Surfactants (e.g. As), deposited on the amorphous germanium, have been used to suppress island formation during solid phase epitaxy on Si. Alternatively, capping the amorphous Ge with a Si layer also suppresses island formation. These measures reduce the surface diffusion of the Ge atoms, consequently suppressing roughening, however the results obtained are not satisfactory.
An improved solid phase epitaxy method for forming a mono-crystalline germanium layer on silicon has been disclosed by the inventors of the present invention in document WO2009/01324208059461. The method describes solid phase epitaxy of germanium on silicon comprising amorphous germanium deposition and thermal anneal in N-containing atmosphere. The mono-crystalline Ge layers obtained are smooth, having a root mean square surface roughness of 0.7 nm (for 100 nm crystallized Ge on Si(111) measured with X-Ray Reflectivity). However, structural investigation by XRD (X-Ray Diffraction) of the samples prepared according to the method above still shows the presence of germanium twins.